Conference Papers:

  1. B.Keng, E.Qin, A.Veneris and B.Le, “Automated Debugging of Missing Assumptions,” in IEEE/ACM Asian-South Pacific Design Automation Conference (ASPDAC), 2014.
  2. B.Keng and A.Veneris, “Automated Debugging of Missing Input Constraints in a Formal Verification Environment,” in Formal Methods in CAD (FMCAD), 2012.
  3. B.Keng and A.Veneris, “Path Directed Abstraction and Refinement in SAT-based Design Debugging,” in IEEE/ACM Design Automation Conference (DAC), 2012.
  4. B.Le, B.Keng, H.Mangassarian and A.Veneris, “Non-Solution Implications using Reverse Domination in a Modern SAT-based Debugging Environment,” in IEEE/ACM Design and Test in Europe (DATE) 2012.
  5. S.Safarpour, B.Keng, Y.-S.Yang, E.Qin, “Failure Triage: The Neglected Debugging Problem,” in Design and Verification Conference (DVCON) 2012.
  6. B.Keng, D.Exon Smith and A.Veneris, “Efficient Debugging of Multiple Design Errors,” in IEEE Microprocessor Test and Verification Workshop (MTV), 2011.
  7. B.Keng, S.Safarpour and A.Veneris, “Automated Debugging of SystemVerilog Assertions,” in IEEE/ACM Design and Test in Europe (DATE), 2011.
  8. A.Veneris, B.Keng and S.Safarpour, “From RTL to Silicon: The Case for Debug Automation,” in IEEE/ACM Asian-South Pacific Design Automation Conference (ASPDAC), 2011 (invited paper).
  9. B.Keng and A.Veneris, “Managing Complexity in Design Debugging with Sequential Abstraction and Refinement,” in IEEE/ACM Asian-South Pacific Design Automation Conference (ASPDAC), 2011.
  10. B.Keng, S. Safarpour and A. Veneris, “An Automated Framework for Correction and Debug of PSL Assertions,” in Microprocessor Test and Verification Workshop (MTV), 2010.
  11. Y.-S.Yang, B. Keng, A.Veneris, N. Nicolici and H. Mangassarian, “Software Solutions to Automating Data Analysis and Acquisition Setup in Silicon Debug,” in IEEE Silicon Debug and Diagnosis Workshop, 2010.
  12. Y.-S.Yang, B.Keng, N.Nicolici, A.Veneris and S.Safarpour, “Automated Silicon Debug Data Analysis Techniques for a Hardware Data Acquisition Environment,” in IEEE International Symposium on Quality of Electronic Design (ISQED), 2010.
  13. B.Keng and A.Veneris, “Scaling VLSI Design Debugging with Interpolation,” in Formal Methods in CAD (FMCAD), 2009.
  14. B.Keng, H.Mangassarian and A.Veneris, “A Succinct Memory Model for Automated Design Debugging,” in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2008.

Journal Papers:

  1. B.Keng and A.Veneris, “Path Directed Abstraction and Refinement in SAT-based Design Debugging,” in IEEE Trans. on CAD, Oct. 2013.
  2. B.Keng, S.Safarpour and A.Veneris, “Bounded Model Debugging,” in IEEE Trans. on CAD, Nov. 2010.

Master’s Thesis:

  • B. Keng, “Scaling SAT-based Automated Design Debugging with Formal Methods,” MASc Thesis, Toronto, 2009.

PhD Thesis:

  • B. Keng, “Advances in Debug Automation for a Modern Verification Environment,” PhD Thesis, Toronto, 2013.

Patents:

  1. B. Keng, E. Kim, “Systems and methods for behavioral segmentation of users in a social data network,” US Patent #9,367,603, Issued June 2016.
  2. E. Kim, B. Keng, K. Padmanabhan, “Systems and methods for dynamically determining influencers in a social data network using weighted analysis,” US Patent #9,262,537, Issued February 2016.
  3. B.Keng, H.Zhou, “Method and apparatus for evaluating the quality of document images,” US Patent #7,689,004, Issued March 2010.
Microprocessor Test and Verification